The present invention refers to an address and break signal generator for generating addresses, by means of which a buffer memory is activated for writing and reading, as well as break signals which are emitted to a sending computer system from which information for controlling a telecommunication equipment is sent to the buffer memory, and which break signals are emitted to a receiving computer system which receives such information from the buffer memory. The two systems each include a clock generator which is controlled by an oscillator of its own and generates a number of mutually phased displaced pulse series and is connected to a pulse treatment circuit in order to, due to break signals, suppress pulses in one of the pulse series which is chosen to indicate timing periods comprising first and second period parts during which the data treatment gives reliable and unreliable results, respectively. The timing periods are used for information transfer if associated pulses are not suppressed by the pulse treatment circuit. Although the oscillators of the computers nominally having the same frequency their frequency spacing gradually changes. It has been known for a long time how to accomplish information transfer between two asynchronously working computers by means of a so called first-in-first-out (FIFO) buffer memory. If the buffer memory has a theoretically infinitely large storing capacity and if the transfer time is allowed to be infinitely long so that this big buffer memory may be half occupied before the first information is read the present asynchronism never causes any information losses due to insufficient buffer capacity or because of the fact that the buffer memory will be so emptied that the writing in of an information word coincides with its reading out. The problem has hithereto demanded an adaption of the buffer capacity and the transfer time to the asynchronism.